Microcomputers are being designed and fabricated as single large scale integrated (LSI) circuit chips including an arithmetic logic unit, a controller, registers, program and data memories and timing circuitry. Typically, such microcomputers use metal oxide semiconductor/large scale integration (MOS/LSI) technology. Other technologies can be and are used.
In prior art microcomputer systems, arrangements are made for performing direct memory access operations. In such an operation, a peripheral device requests that a transfer of information be made between the peripheral device and the memory of the microcomputer. The central processor of the microcomputer suspends operation for a cycle at a time, and the information is transferred directly from the peripheral device to the memory or viceversa without passing through the arithmetic logic unit of the main processor and without being controlled by the central processing unit.
Such a direct memory access operation is controlled by special circuitry that is separate from the main processor arrangement. A general description of a direct memory access arrangement is presented by A. Osborne in An Introduction to Microcomputers Vol. 1, 1976, pages 5-34 to 5-41. The direct memory access controller generates addresses for the direct memory access operations. The special circuitry described there includes an address register, a counter register, and an incrementing or decrementing circuit. It is noted that this circuitry is separate from and therefore in addition to the circuitry of the main processor.
The main processor generates addresses for use in processing routine instructions. In the main processor, there is an address register and an incrementing or decrementing circuit for performing address operations in processing the routine instructions.
Thus the prior art direct memory access arrangement includes duplicate address register and incrementing or decrementing circuits, one in the main processor and another in the direct memory access controller. When built in LSI chips, this presents a problem because the duplication requires extra chip area which increases the cost of the chip because fewer chips fit on a wafer and the yield of good chips from each wafer is reduced.